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Serial UART information

Serial UART, an introduction

A UART, universal asynchronous receiver / transmitter is responsible for performing the main task in serial communications with computers. The device changes incomming parallel information to serial data which can be sent on a communication line. A second UART can be used to receive the information. The UART performs all the tasks, timing, parity checking, etc. needed for the communication. The only extra devices attached are line driver chips capable of transforming the TTL level signals to line voltages and vice versa.

To use the UART in different environments, registers are accessible to set or review the communication parameters. Setable parameters are for example the communication speed, the type of parity check, and the way incomming information is signalled to the running software.

Serial UART types

Serial communication on PC compatibles started with the 8250 UART in the IBM XT. In the years after, new family members were introduced like the 8250A and 8250B revisions and the 16450. The last one was first implemented in the AT. The higher bus speed in this computer could not be reached by the 8250 series. The differences between these first UART series were rather minor. The most important property changed with each new release was the maximum allowed speed at the processor bus side.

The 16450 was capable of handling a communication speed of 38.4 kbs without problems. The demand for higher speeds led to the development of newer series which would be able to release the main processor from some of its tasks. The main problem with the original series was the need to perform a software action for each single byte to transmit or receive. To overcome this problem, the 16550 was released which contained two on-board FIFO buffers, each capable of storing 16 bytes. One buffer for incomming, and one buffer for outgoing bytes.

A marvellous idea, but it didn't work out that way. The 16550 chip contained a firmware bug which made it impossible to use the buffers. The 16550A which appeared soon after was the first UART which was able to use its FIFO buffers. This made it possible to increase maximum reliable communication speeds to 115.2 kbs. This speed was necessary to use effectively modems with on-board compression. A further enhancment introduced with the 16550 was the ablity to use DMA, direct memory access for the data transfer. Two pins were redefined for this purpose. DMA transfer is not used with most applications. Only special serial I/O boards with a high number of ports contain sometimes the necessary extra circuitry to make this feature work.

The 16550A is the most common UART at this moment. Newer versions are under development, including the 16650 which contains two 32 byte FIFO's and on board support for software flow control. Texas Instruments is developing the 16750 which contains 64 byte FIFO's.

Registers

Eight I/O bytes are used for each UART to access its registers. The following table shows, where each register can be found. The base address used in the table is the lowest I/O port number assigned. The switch bit DLAB can be found in the line control register LCR as bit 7 at I/O address base + 3.

UART register to port conversion table
 DLAB = 0DLAB = 1
I/O portReadWriteReadWrite
baseRBR
receiver
buffer
THR
transmitter
holding
DLL divisor latch LSB
base + 1IER
interrupt
enable
IER
interrupt
enable
DLM divisor latch MSB
base + 2IIR
interrupt
identification
FCR
FIFO
control
IIR
interrupt
identification
FCR
FIFO
control
base + 3LCR line control
base + 4MCR modem control
base + 5LSR
line
status

factory
test
LSR
line
status

factory
test
base + 6MSR
modem
status

not
used
MSR
modem
status

not
used
base + 7SCR scratch

Available registers
RBR, receiver buffer register
THR, transmitter holding register
IER, interrupt enable register
IIR, interrupt identification register
FCR, FIFO control register
LCR, line control register
MCR, modem control register
LSR, line status register
MSR, modem status register
SCR, scratch register
DLL, divisor latch LSB
DLM, divisor latch MSB

The communication between the processor and the UART is completely controlled by twelve registers. These registers can be read or written to check and change the behaviour of the communication device. Each register is eight bits wide. On a PC compatible, the registers are accessible in the I/O address area. The function of each register will be discussed here in detail.

RBR : Receiver buffer register (RO)

The RBR, receiver buffer register contains the byte received if no FIFO is used, or the oldest unread byte with FIFO's. If FIFO buffering is used, each new read action of the register will return the next byte, until no more bytes are present. Bit 0 in the LSR line status register can be used to check if all received bytes have been read. This bit wil change to zero if no more bytes are present.

THR : Transmitter holding register (WO)

The THR, transmitter holding register is used to buffer outgoing characters. If no FIFO buffering is used, only one character can be stored. Otherwise the amount of characters depends on the type of UART. Bit 5 in the LSR, line status register can be used to check if new information must be written to THR. The value 1 indicates that the register is empty. If FIFO buffering is used, more than one character can be written to the transmitter holding register when the bit signals an empty state. There is no indication of the amount of bytes currently present in the transmitter FIFO.

The transmitter holding register is not used to transfer the data directly. The byte is first transferred to a shift register where the information is broken in single bits which are sent one by one.

IER : Interrupt enable register (R/W)

The smartest way to perform serial communications on a PC is using interrupt driven routines. In that configuration, it is not necessary to poll the registers of the UART periodically for state changes. The UART will signal each change by generating a processor interrupt. A software routine must be present to handle the interrupt and to check what state change was responsible for it.

Interrupts are not generated, unless the UART is told to do so. This is done by setting bits in the IER, interrupt enable register. A bit value 1 indicates, that an interrupt may take place.

IER : Interrupt enable register
BitDescription
0Received data available
1Transmitter holding register empty
2Receiver line status register change
3Modem status register change
4Sleep mode (16750 only)
5Low power mode (16750 only)
6reserved
7reserved

IIR : Interrupt identification register (RO)

A UART is capable of generating a processor interrupt when a state change on the communication device occurs. One interrupt signal is used to call attention. This means, that additional information is needed for the software before the necessary actions can be performed. The IIR, interrupt identification register is helpful in this situation. Its bits show the current state of the UART and which state change caused the interrupt to occur.

IIR : Interrupt identification register
BitValueDescriptionReset by
00Interrupt pending
1No interrupt pending
1,2,3Bit 3Bit 2Bit 1  
000Modem status changeMSR read
001Transmitter holding register emptyIIR read or THR write
010Received data availableRBR read
011Line status changeLSR read
110Character timeout (16550)RBR read
40Reserved
50Reserved (8250, 16450, 16550)
164 byte FIFO enabled (16750)
6,7Bit 7Bit 6  
00No FIFO
10Unusable FIFO (16550 only)
11FIFO enabled

FCR : FIFO control register (WO)

The FCR, FIFO control register is present starting with the 16550 series. This register controls the behaviour of the FIFO's in the UART. If a logical value 1 is written to bits 1 or 2, the function attached is triggered. The other bits are used to select a specific FIFO mode.

FCR : FIFO control register
BitValueDescription
00Disable FIFO's
1Enable FIFO's
10
1Clear receive FIFO
20
1Clear transmit FIFO
30Select DMA mode 0
1Select DMA mode 1
40Reserved
50Reserved (8250, 16450, 16550)
1Enable 64 byte FIFO (16750)
6,7Bit 7Bit 6Receive FIFO interrupt trigger level
001 byte
014 bytes
108 bytes
1114 bytes

LCR : Line control register (R/W)

The LCR, line control register is used at initialisation to set the communication parameters. Parity and number of data bits can be changed for example. The register also controls the accessibility of the DLL and DLM registers. These registers are mapped to the same I/O port as the RBR, THR and IER registers. Because they are only accessed at initialisation when no communication occurs this register swapping has no influence on performance.

LCR : line control register
BitValueDescription
0,1Bit 1Bit 0Data word length
005 bits
016 bits
107 bits
118 bits
201 stop bit
11.5 stop bits (5 bits word)
2 stop bits (6, 7 or 8 bits word)
3,4,5Bit 5Bit 4Bit 3 
xx0No parity
001Odd parity
011Even parity
101High parity (stick)
111Low parity (stick)
60Break signal disabled
1Break signal enabled
70DLAB : RBR, THR and IER accessible
1DLAB : DLL and DLM accessible

Some remarks about parity:

The UART is capable of generating a trailing bit at the end of each dataword which can be used to check some data distortion. Because only one bit is used, the parity system is capable of detecting only an odd number of false bits. If an even number of bits has been flipped, the error will not be seen.

When even parity is selected, the UART assures that the number of high bit values in the sent or received data is always even. Odd parity setting does the opposite. Using stick parity has very little use. It sets the parity bit to always 1, or always 0.

Common settings are:

  • 8 data bits, one stop bit, no parity
  • 7 data bits, one stop bit, even parity

MCR : Modem control register (R/W)

The MCR, modem control register is used to perform handshaking actions with the attached device. In the original UART series including the 16550, setting and resetting of the control signals must be done by software. The new 16750 is capable of handling flow control automatically, thereby reducing the load on the processor.

MCR : Modem control register
BitDescription
0Data terminal ready
1Request to send
2Auxiliary output 1
3Auxiliary output 2
4Loopback mode
5Autoflow control (16750 only)
6Reserved
7Reserved

The two auxiliary outputs are user definable. Output 2 is sometimes used in circuitry which controls the interrupt process on a PC. Output 1 is normally not used, however on some I/O cards, it controls the selection of a second oscillator working at 4 MHz. This is mainly for MIDI purposes.

LSR : Line status register (RO)

The LSR, line status register shows the current state of communication. Errors are reflected in this register. The state of the receive and transmit buffers is also available.

LSR : Line status register
BitDescription
0Data available
1Overrun error
2Parity error
3Framing error
4Break signal received
5THR is empty
6THR is empty, and line is idle
7Errornous data in FIFO

Bit 5 and 6 both show the state of the transmitting cycle. The difference is, that bit 5 turns high as soon as the transmitter holding register is empty whereas bit 6 indicates that also the shift register which outputs the bits on the line is empty.

MSR : Modem status register (RO)

The MSR, modem status register contains information about the four incomming modem control lines on the device. The information is split in two nibbles. The four most siginificant bits contain information about the current state of the inputs where the least significant bits are used to indicate state changes. The four LSB's are reset, each time the register is read.

MSR : Modem status register
BitDescription
0change in Clear to send
1change in Data set ready
2trailing edge Ring indicator
3change in Carrier detect
4Clear to send
5Data set ready
6Ring indicator
7Carrier detect

SCR : Scratch register (R/W)

The SCR, scratch register was not present on the 8250 and 8250B UART. It can be used to store one byte of information. In practice, it has only limited use. The only real use I know of is checking if the UART is a 8250/8250B, or a 8250A/16450 series. Because the 8250 series are only found in XT's even this use of the register is not commonly seen anymore.

DLL and DLM : Divisor latch registers (R/W)

For generating its timing information, each UART uses an oscillator generating a frequency of about 1.8432 MHz. This frequency is divided by 16 to generate the time base for communucation. Because of this division, the maximum allowed communication speed is 115200 bps. Modern UARTS like the 16550 are capable of handling higher input frequencies up to 24 MHz which makes it possible to communicate with a maximum speed of 1.5 Mbps. On PC's higher frequencies than the 1.8432 MHz are rarely seen because this would be software incompatible with the original XT configuration.

This 115200 bps communication speed is not suitable for all applications. To change the communication speed, the frequency can be further decreased by dividing it by a programmable value. For very slow communications, this value can go beyond 255. Therefore, the divisor is stored in two seperate bytes, the divisor latch registers DLL and DLM which contain the least, and most significant byte.

For error free communication, it is necessary that both the transmitting and receiving UART use the same time base. Default values have been defined which are commonly used. The table shows the most common values with the appropriate settings of the divisor latch bytes. Note that these values only hold for a PC compatible system where a clock frequency of 1.8432 MHz is used.

DLL and DLM : Divisor latch registers
Speed (bps)DivisorDLLDLM
502,3040x000x09
3003840x800x01
1,200960x600x00
2,400480x300x00
4,800240x180x00
9,600120x0C0x00
19,20060x060x00
38,40030x030x00
57,60020x020x00
115,20010x010x00

Before God we are all equally wise;
and equally foolish.
ALBERT EINSTEIN
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