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modbus crc in verilog


 

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feir
New User



Joined: 03 May 2013
Posts: 2
Location: Germany

May 03, 2013 7:51 am

Hey guys,
I use OutpuLogic to generate the Verilog code for modbus rtu crc, but it doesn't work at all. the crc results from my code is very different to the results from this online caculator. can somebody give me some tipps?

// CRC module for data[7:0] , crc[15:0]=1+x^2+x^15+x^16;
//-----------------------------------------------------------------------------
module crc(
input [7:0] data_in,
input crc_en,
output [15:0] crc_out,
input rst,
input clk);

reg [15:0] lfsr_q,lfsr_c;

assign crc_out = lfsr_q;

always @(*) begin
lfsr_c[0] = lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
lfsr_c[1] = lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];
lfsr_c[2] = lfsr_q[8] ^ lfsr_q[9] ^ data_in[0] ^ data_in[1];
lfsr_c[3] = lfsr_q[9] ^ lfsr_q[10] ^ data_in[1] ^ data_in[2];
lfsr_c[4] = lfsr_q[10] ^ lfsr_q[11] ^ data_in[2] ^ data_in[3];
lfsr_c[5] = lfsr_q[11] ^ lfsr_q[12] ^ data_in[3] ^ data_in[4];
lfsr_c[6] = lfsr_q[12] ^ lfsr_q[13] ^ data_in[4] ^ data_in[5];
lfsr_c[7] = lfsr_q[13] ^ lfsr_q[14] ^ data_in[5] ^ data_in[6];
lfsr_c[8] = lfsr_q[0] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[6] ^ data_in[7];
lfsr_c[9] = lfsr_q[1] ^ lfsr_q[15] ^ data_in[7];
lfsr_c[10] = lfsr_q[2];
lfsr_c[11] = lfsr_q[3];
lfsr_c[12] = lfsr_q[4];
lfsr_c[13] = lfsr_q[5];
lfsr_c[14] = lfsr_q[6];
lfsr_c[15] = lfsr_q[7] ^ lfsr_q[8] ^ lfsr_q[9] ^ lfsr_q[10] ^ lfsr_q[11] ^ lfsr_q[12] ^ lfsr_q[13] ^ lfsr_q[14] ^ lfsr_q[15] ^ data_in[0] ^ data_in[1] ^ data_in[2] ^ data_in[3] ^ data_in[4] ^ data_in[5] ^ data_in[6] ^ data_in[7];

end // always

always @(posedge clk, posedge rst) begin
if(rst) begin
lfsr_q <= {16{1'b1}};
end
else begin
lfsr_q <= crc_en ? lfsr_c : lfsr_q;
end
end // always
endmodule // crc
feir
New User



Joined: 03 May 2013
Posts: 2
Location: Germany

May 07, 2013 9:30 am

change 15-0 to 0-15 and 7-0 to 0-7 then it works
sergey
Guest







Oct 30, 2013 9:06 pm

Hi.
solved this problem?

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