Joined: 09 Oct 2014
|Oct 09, 2014 5:05 pm
I am a verification engineer, but I have not yet touched CRC - so please forgive my lack of knowledge. Pointers to good documentation are welcome.
I shall verify a given hardware CRC implementation. The only specifications I have are:
16bit CRC, 44bit input data width, polynom: 0xC86C, is able to be pre-loaded with a previous CRC computation result.
My approach was to build a reference CRC implementation for my test bench. This one would be a serial CRC computation in contrast to the parallel CRC computation of the hardware. OK, I could also only copy the "tons of XOR gates" of the hardware implementation, but this could then not be called verification, right?
While implementing my reference model, I came along following questions:
is polynom applied MSB first?
is data shifted in MSB first?
is CRC result modified in some way?
My question to you is: what else is missing in the specification when I barely got more than "0xC86C".
Or: how can I proof that the given sea of XOR gates is not implementing "0xC86C" CRC?