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VHDL CRC generator


 

       Computer Interfacing Forum Index -> Error detection and correction
Author Message
klapa
Junior Member



Joined: 24 May 2007
Posts: 12
Location: Cary, NC, USA

Jan 18, 2008 7:34 pm

All,

I don't know if any would benifit from this but thought I would post it.

This is a VHDL implementation of the CRC-CCITT algorithm. It would be easy to modify this simple routine to accommodate any word width and polynomial desired.

For the receiver - the same operations are performed - only to include the received CRC - the final value is checked to be "zero" for no error indication.

Code:

-------------------------------------------------------------------------
-- 16-bit Serial CRC-CCITT Generator.
-------------------------------------------------------------------------
library ieee;

use ieee.std_logic_1164.all;

entity crc16 is
   port (clk, reset, ce, din: in std_logic;
        crc_sum: out std_logic_vector(15 downto 0));
       end crc16;
      
architecture behavior of crc16 is
    signal X: std_logic_vector(15 downto 0);
   
begin
    reg:process(reset, clk, ce)
    begin
      if  reset = '1' then
         X(15)  <= '1';
         X(14)  <= '1';
         X(13)  <= '1';
         X(12)  <= '1';
         X(11)  <= '1';
         X(10)  <= '1';
         X(9)  <= '1';
         X(8)  <= '1';
         X(7)  <= '1';
         X(6)  <= '1';
         X(5)  <= '1';
         X(4)  <= '1';
         X(3)  <= '1';
         X(2)  <= '1';
         X(1)  <= '1';
         X(0)  <= '1';
      elsif ce = '1' then
         if rising_edge(clk) then
               X(0)  <= Din  xor X(15);
               X(1)  <= X(0);
               X(2)  <= X(1);
               X(3)  <= X(2);
               X(4)  <= X(3);
               X(5)  <= X(4) xor (din xor X(15));
               X(6)  <= X(5);
            X(7)  <= X(6);
               X(8)  <= X(7);
               X(9)  <= X(8);
               X(10)  <= X(9);
               X(11)  <= X(10);
               X(12)  <= X(11) xor (din xor X(15));
               X(13)  <= X(12);
               X(14)  <= X(13);
            X(15)  <= X(14);
           end if;
        end if;
    end process;
    crc_sum <= X;
end behavior;
khwoo08
Guest







Sep 23, 2010 6:41 am

can you please explain for the two block processes? thanks
Guest








Mar 02, 2013 7:13 pm

You can replace

X(15) <= '1';
X(14) <= '1';
X(13) <= '1';
.
.
.
X(0) <= '1';

by

X <= (others => '1');
Guest








Dec 23, 2014 5:17 pm

PLEASE EXPLAIN THE ABOVE CODE.PLEASE.
Guest








Dec 23, 2014 5:18 pm

I MEAN FOR THE CRC-16 GENERATOR

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